项目

1. 国家自然科学基金面上项目，基于FPGA的卷积神经网络系统可靠性及加固技术研究，参与，经费数额：64万。
2. 横向项目，单粒子效应容错技术研究及软件开发，参与，经费数额：20万。

论文

l 期刊论文
[1] Gao, Zhen; Wang, Jingyan; Wang, Ruize; Zhu, Jinhua*. " Reliability Evaluation and Efficient Protection of FPGA based Polar Decoders against Single Event Upsets on Configuration Memory," in China Communications. 2024. SCI三区.
[2] Gao, Zhen; Zhu, Jinhua*; Reviriego, Pedro. "Reliability Evaluation and Fault Tolerant Design for KLL Sketches," in IEEE Transactions on Emerging Topics in Computing, 2023. SCI二区.
[3] Gao, Zhen; Zhu, Jinhua; Yan, Tong; Ullah, Anees; Reviriego, Pedro. "Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations," in IEEE Transactions on Emerging Topics in Computing, 2022. SCI二区.
[4] Zhu, Jinhua; Jin, Jie; Gao, Zhen; Reviriego, Pedro. "Single Event Transient tolerant Count Min Sketches," in Microelectronics Reliability, 2022. SCI四区.
[5] Gao, Zhen; Zhu, Jinhua; Yan, Tong; Guo, Linghua; Chen, Xiangping; Li, Yinqiao; Wan, Xiaolei. "Fault tolerant design of large-scale digital beam forming in SRAM-FPGAs for software defined satellite platforms," in China Communications, 2020. SCI三区.
[6] Gao, Zhen; Yan, Lina; Zhu, Jinhua*; Han, Ruishi; Ullah, Anees; Reviriego, Pedro. "Radiation tolerant viterbi decoders for on-board processing (OBP) in satellite communications," in China Communications, 2020. SCI 三区.
[7] Gao, Zhen; Zhu, Jinhua; Han, Ruishi; Xu, Zhan; Ullah, Anees; Reviriego, Pedro. "Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs," in IEEE Transactions on Nanotechnology, 2019. SCI三区.
l 会议论文
[1] Zhu, Jinhua; Gao, Zhen; Jin, Jie; Reviriego, Pedro. Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs)," 2021 IEEE 39th VLSI Test Symposium (VTS), 2021.
[2] Gao, Zhen; Zhu, Jinhua; Yan, Lina; Yan, Tong; Reviriego, Pedro. "Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs," 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019.
[3] Gao, Zhen; Yan, Lina; Zhu, Jinhua; Han, Ruishi; Reviriego, Pedro. "Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders," 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018.

专利

l 一种基于线性编码的并行线性处理系统的容错方法, CN111176881B. 第二发明人